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DSP56F805/d rev. 7.0 , 1/2002 ? motorola, inc., 2002. all rights reserved. dsp56f80 5 preliminary technical data DSP56F805 16-bit digital signal processor ? up to 40 mips at 80 mhz core frequency ? dsp and mcu functionality in a unified, c-efficient architecture ? hardware do and rep loops ? mcu-friendly instruction set supports both dsp and controller functions: mac, bit manipulation unit, 14 addressing modes ?31.5k 16-bit words program flash ? 512 16-bit words program ram ?4k 16-bit words data flash ?2k 16-bit words data ram ?2k 16-bit words boot flash ? up to 64k 16-bit words each of external program and data memory ? two 6-channel pwm modules ? two 4-channel, 12-bit adcs ? two quadrature decoders ? can 2.0 b module ? two serial communication interfaces (scis) ? serial peripheral interface (spi) ? up to four general purpose quad timers ?jtag/once tm port for debugging ? 14 dedicated and 18 shared gpio lines ? 144-pin lqfp package figure 1. DSP56F805 block diagram jtag/ once port digital reg analog reg low voltage supervisor program controller and hardware looping unit data alu 16 x 16 + 36 ? 36-bit mac three 16-bit input registers two 36-bit accumulators address generation unit bit manipulation unit pll clock gen 16-bit dsp56800 core pab pdb xdb2 cgdb xab1 xab2 xtal extal interrupt controls ipbb controls ipbus bridge (ipbb) module controls address bus [8:0] data bus [15:0] cop reset reset irqa irqb application- specific memory & peripherals interrupt controller program memory 32252 x 16 flash 512 x 16 sram boot flash 2048 x 16 flash data memory 4096 x 16 flash 2048 x 16 sram cop/ watchdog spi or gpio sci0 or gpio quad timer d / alt func quad timer c a/d1 a/d2 adc 4 2 4 4 4 4 6 pwm outputs fault inputs pwma 16 16 vcapc v dd v ss v dda v ssa 6 28 8* extboot current sense inputs 3 quadrature decoder 0/ quad timer a can 2.0a/b 2 clko external address bus switch bus control external data bus switch external bus interface unit rd enable wr enable ds select ps select 10 16 6 a[00:05] d[00:15] a[06:15] or gpio-e2:e3 & gpio-a0:a7 4 4 6 pwm outputs fault inputs pwmb current sense inputs 3 quadrature decoder 1/ quad b timer 4 2 sci1 or gpio 2 dedicated gpio 14 vpp rsto vref * includes tcs pin which is reserved for factory use and is tied to vss
2 DSP56F805 preliminary technical data motorola part 1 overview 1.1 DSP56F805 features 1.1.1 digital signal processing core ? efficient 16-bit dsp56800 family dsp engine with dual harvard architecture ? as many as 40 million instructions per second (mips) at 80 mhz core frequency ? single-cycle 16 16-bit parallel multiplier-accumulator (mac) ? two 36-bit accumulators, including extension bits ? 16-bit bidirectional barrel shifter ? parallel instruction set with unique dsp addressing modes ? hardware do and rep loops ? three internal address buses and one external address bus ? four internal data buses and one external data bus ? instruction set supports both dsp and controller functions ? controller style addressing modes and instructions for compact code ? efficient c compiler and local variable support ? software subroutine and interrupt stack with depth limited only by memory ? jtag/once debug programming interface 1.1.2 memory ? harvard architecture permits as many as three simultaneous accesses to program and data memory ? on-chip memory including a low cost, high volume flash solution 31.5k 16 bit words of program flash 512 16-bit words of program ram 4k 16-bit words of data flash 2k 16-bit words of data ram 2k 16-bit words of boot flash ? off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states as much as 64k 16 bits of data memory as much as 64k 16 bits of program memory 1.1.3 peripheral circuits for DSP56F805 ? two pulse width modulator modules each with six pwm outputs, three current sense inputs, and four fault inputs, fault tolerant design with dead-time insertion; supports both center- and edge- aligned modes ? two 12-bit analog-to-digital converters (adc) which support two simultaneous conversions; adc and pwm modules can be synchronized ? two quadrature decoders each with four inputs or two additional quad timers
DSP56F805 description motorola DSP56F805 preliminary technical data 3 ? two general purpose quad timers totaling six pins: timer c with two pins and timer d with four pins ? can 2.0 b module with 2-pin port for transmit and receive ? two serial communication interfaces, each with two pins (or four additional gpio lines) ? serial peripheral interface (spi) with configurable four-pin port (or four additional gpio lines) ? 14 dedicated general purpose i/o (gpio) pins, 18 multiplexed gpio pins ? computer operating properly (cop) watchdog timer ? two dedicated external interrupt pins ? external reset input pin for hardware reset ? external reset output pin for system reset ? jtag/on-chip emulation (once?) module for unobtrusive, processor speed-independent debugging ? software-programmable, phase lock loop-based frequency synthesizer for the dsp core clock 1.1.4 energy information ? fabricated in high-density cmos with 5v tolerant, ttl-compatible digital inputs ? uses a single 3.3v power supply ? on-chip regulators for digital and analog circuitry to lower cost and reduce noise ? wait and stop modes available 1.2 DSP56F805 description the DSP56F805 is a member of the dsp56800 core-based family of digital signal processors (dsps). it combines, on a single chip, the processing power of a dsp and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. because of its low cost, configuration flexibility, and compact program code, the DSP56F805 is well-suited for many applications. the DSP56F805 includes many peripherals that are especially useful for applications such as motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control, automotive control, engine management, noise suppression, remote utility metering, and industrial control for power, lighting, and automation. the dsp56800 core is based on a harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. the microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both mcu and dsp applications. the instruction set is also highly efficient for c compilers to enable rapid development of optimized control applications. the DSP56F805 supports program execution from either internal or external memories. two data operands can be accessed from the on-chip data ram per instruction cycle. the DSP56F805 also provides two external dedicated interrupt lines, and up to 32 general purpose input/output (gpio) lines, depending on peripheral configuration. the DSP56F805 dsp controller includes 31.5k words (16-bit) of program flash and 4k words of data flash (each programmable through the jtag port) with 512 words of program ram and 2k words of data ram. it also supports program execution from external memory (64k).
4 DSP56F805 preliminary technical data motorola the DSP56F805 incorporates a total of 2k words of boot flash for easy customer-inclusion of field- programmable software routines that can be used to program the main program and data flash memory areas. both program and data flash memories can be independently bulk-erased or erased in page sizes of 256 words. the boot flash memory can also be either bulk- or page-erased. key application-specific features of the DSP56F805 include the two pulse width modulator (pwm) modules. these modules each incorporate three complementary, individually programmable pwm signal outputs (each module is also capable of supporting six independent pwm functions for a total of 12 pwm outputs) to enhance motor control functionality. complementary operation permits programmable dead- time insertion, distortion correction via current sensing by software, and separate top and bottom output polarity control. the up-counter value is programmable to support a continuously variable pwm frequency. edge- and center-aligned synchronous pulse width control (0% to 100% modulation) is supported. the device is capable of controlling most motor types: acim (ac induction motors), both bdc and bldc (brush and brushless dc motors), srm and vrm (switched and variable reluctance motors), and stepper motors. the pwms incorporate fault protection and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard opto-isolators. a smoke-inhibit, write- once protection feature for key parameters and a patented pwm waveform distortion correction circuit are also provided. each pwm is double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1 to 16. the pwm modules provide a reference output to synchronize the adcs. the DSP56F805 incorporates two separate quadrature decoders capable of capturing all four transitions on the two-phase inputs, permitting generation of a number proportional to actual position. speed computation capabilities accommodate both fast and slow moving shafts. the integrated watchdog timer in the quadrature decoder can be programmed with a timeout value to alarm when no shaft motion is detected. each input is filtered to ensure only true transitions are recorded. this dsp controller also provides a full set of standard programmable peripherals that include two serial communications interfaces (sci), one serial peripheral interface (spi), and four quad timers. any of these interfaces can be used as general purpose input/outputs (gpios) if that function is not required. a controller area network interface (can version 2.0 a/b-compliant), an internal interrupt controller and 14 dedicated gpio are also included on the DSP56F805. 1.3 best in class development environment the sdk (software development kit) provides fully debugged peripheral drivers, libraries and interfaces that allow programmers to create their unique c application code independent of component architecture. the codewarrior integrated development environment is a sophisticated tool for code navigation, compiling, and debugging. a complete set of evaluation modules (evms) and development system cards support concurrent engineering. together, the sdk, codewarrior, and evms create a complete, scalable tools solution for easy, fast, and efficient development.
product documentation motorola DSP56F805 preliminary technical data 5 1.4 product documentation the four documents listed in table 1 are required for a complete description and proper design with the DSP56F805. documentation is available from local motorola distributors, motorola semiconductor sales offices, motorola literature distribution centers, or online at www.motorola.com/semiconductors/dsp . table 1. DSP56F805 chip documentation 1.5 data sheet conventions this data sheet uses the following conventions: topic description order number dsp56800 family manual detailed description of the dsp56800 family architecture, and 16-bit dsp core processor and the instruction set dsp56800fm/d dsp56f801/803/805/ 807 users manual detailed description of memory, peripherals, and interfaces of the dsp56f801, dsp56f803, DSP56F805, and dsp56f807 dsp56f801-7um/d DSP56F805 technical data sheet electrical and timing specifications, pin descriptions, and package descriptions (this document) DSP56F805/d DSP56F805 product brief summary description and block diagram of the DSP56F805 core, memory, peripherals and interfaces DSP56F805pb/d overbar this is used to indicate a signal that is active when pulled low. for example, the reset pin is active when low. asserted a high true (active high) signal is high or a low true (active low) signal is low. deasserted a high true (active high) signal is low or a low true (active low) signal is high. examples: signal/symbol logic state signal state voltage 1 1. values for vil, vol, vih, and voh are defined by individual product specifications. pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol
6 DSP56F805 preliminary technical data motorola part 2 signal/connection descriptions 2.1 introduction the input and output signals of the DSP56F805 are organized into functional groups, as shown in table 2 and as illustrated in figure 2 . in table 3 through table 19 , each table row describes the signal or signals present on a pin. table 2. functional group pin allocations functional group number of pins detailed description power (v dd or v dda )9 table 3 ground (v ss or v ssa )9 table 4 supply capacitors and v pp 3 table 5 pll and clock 3 table 2.3 address bus 1 16 table 7 data bus 16 table 8 bus control 4 table 9 interrupt and program control 5 table 10 dedicated general purpose input/output 14 table 11 pulse width modulator (pwm) port 26 table 12 serial peripheral interface (spi) port 1 1. alternately, gpio pins 4 table 13 quadrature decoder port 2 2. alternately, quad timer pins 8 table 14 serial communications interface (sci) port 1 4 table 15 can port 2 table 16 analog to digital converter (adc) port 9 table 17 quad timer module ports 6 table 18 jtag/on-chip emulation (once) 6 table 19
introduction motorola DSP56F805 preliminary technical data 7 figure 2. DSP56F805 signals identified by functional group 1 1. alternate pin functionality is shown in parenthesis. DSP56F805 power port ground port power port ground port pll and clock external address bus or gpio external data bus external bus control dedicated gpio sci0 port or gpio sci1 port or gpi0 v dd v ss v dda v ssa vcapc v pp extal xtal clko a0-a5 a6-7 (gpioe2-e3) a8-15 (gpioa0-a7) d0Cd15 ps ds rd wr phasea0 (ta0) phaseb0 (ta1) index0 (ta2) home0 (ta3) phasea1 (tb0) phaseb1 (tb1) index1 (tb2) home1 (tb3) tck tms tdi tdo trst de quadrature decoder0 or quad timer a jtag/once ? port gpiob0C7 gpiod0C5 pwma0-5 isa0-2 faulta0-3 pwmb0-5 isb0-2 faultb0-3 sclk (gpioe4) mosi (gpioe5) miso (gpioe6) ss (gpioe7) txd0 (gpioe0) rxd0 (gpioe1) txd1 (gpiod6) rxd1 (gpiod7) ana0-7 vref mscan_rx mscan_tx tc0-1 td0-3 irqa irqb reset rsto extboot pwmb port quad timers c & d adca port other supply ports 8 8* 1 1 2 1 1 1 1 6 2 8 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 interrupt/ program control 8 6 6 3 4 6 3 4 1 1 1 1 1 1 1 1 8 1 1 1 2 4 1 1 1 1 1 quadrature decoder1 or quad timer b pwma port spi port or gpio can * includes tcs pin which is reserved for factory use and is tied to vss
8 DSP56F805 preliminary technical data motorola 2.2 power and ground signals 2.3 clock and phase lock loop signals table 3. power inputs no. of pins signal name signal description 8 v dd power these pins provide power to the internal structures of the chip, and should all be attached to v dd. 1 v dda analog power these pins supply an analog power source. table 4. grounds no. of pins signal name signal description 7 v ss gnd these pins provide grounding for the internal structures of the chip, and should all be attached to v ss. 1 v ssa analog ground this pin supplies an analog ground. 1 tcs tcs this pin is reserved for factory use and must be tied to v ss for normal use. in block diagrams, this pin is considered an additional v ss. table 5. supply capacitors and vpp no. of pins signal name signal type state during reset signal description 2 vcapc supply supply vcapc - connect each pin to a 2.2 m f bypass capacitor in order to bypass the core logic voltage regulator, required for proper chip operation. for more information, please refer to section 5.2 . 1 vpp input input vpp - this pin should be left unconnected as an open circuit for normal functionality. table 6. pll and clock no. of pins signal name signal type state during reset signal description 1 extal input input external crystal oscillator input this input should be connected to an 8 mhz external crystal or ceramic resonator. for more information, please refer to section 3.5 . 1 xtal input/ output chip-driven crystal oscillator output this output should be connected to an 8 mhz external crystal or ceramic resonator. for more information, please refer to section 3.5 . this pin can also be connected to an external clock source. for more information, please refer to section 3.5.3 .
address, data, and bus control signals motorola DSP56F805 preliminary technical data 9 2.4 address, data, and bus control signals 1 clko output chip-driven clock output this pin outputs a buffered clock signal. by programming the cloksel[4:0] bits in the clko select register (clkosr), the user can select between outputting a version of the signal applied to xtal and a version of the dsp master clock at the output of the pll. the clock frequency on this pin can also be disabled by programming the cloksel[4:0] bits in clkosr. table 7. address bus signals no. of pins signal name signal type state during reset signal description 6 a0Ca5 output tri-stated address bus a0Ca5 specify the address for external program or data memory accesses. 2 a6Ca7 gpioe2 C gpioe3 output input/ output tri-stated input address bus a6Ca7 specify the address for external program or data memory accesses. port e gpio these two general purpose i/o (gpio) pins can be individually programmed as input or output pins. after reset, the default state is address bus. 8 a8Ca15 gpioa0 C gpioa7 output input/ output tri-stated input address bus a8Ca15 specify the address for external program or data memory accesses. port a gpio these eight general purpose i/o (gpio) pins can be individually be programmed as input or output pins. after reset, the default state is address bus. table 8. data bus signals no. of pins signal name signal type state during reset signal description 16 d0Cd15 input/ output tri-stated data bus d0Cd15 specify the data for external program or data memory accesses. d0Cd15 are tri-stated when the external bus is inactive. table 6. pll and clock (continued) no. of pins signal name signal type state during reset signal description
10 DSP56F805 preliminary technical data motorola 2.5 interrupt and program control signals table 9. bus control signals no. of pins signal name signal type state during reset signal description 1 ps output tri-stated program memory select ps is asserted low for external program memory access. 1 ds output tri-stated data memory select ds is asserted low for external data memory access. 1 wr output tri-stated write enable wr is asserted during external memory write cycles. when wr is asserted low, pins d0Cd15 become outputs and the dsp puts data on the bus. when wr is deasserted high, the external data is latched inside the external device. when wr is asserted, it qualifies the a0Ca15, ps , and ds pins. wr can be connected directly to the we pin of a static ram. 1 rd output tri-stated read enable rd is asserted during external memory read cycles. when rd is asserted low, pins d0Cd15 become inputs and an external device is enabled onto the dsp data bus. when rd is deasserted high, the external data is latched inside the dsp. when rd is asserted, it qualifies the a0Ca15, ps , and ds pins. rd can be connected directly to the oe pin of a static ram or rom. internal pullups may be active. table 10. interrupt and program control signals no. of pins signal name signal type state during reset signal description 1 irqa input input external interrupt request a the irqa input is a synchronized external interrupt request indicating an external device is requesting service. it can be programmed to be level-sensitive or negative-edge- triggered. 1 irqb input input external interrupt request b the irqb input is an external interrupt request indicating an external device is requesting service. it can be programmed to be level-sensitive or negative-edge-triggered. 1 reset input input reset this input is a direct hardware reset on the processor. when reset is asserted low, the dsp is initialized and placed in the reset state. a schmitt trigger input is used for noise immunity. when the reset pin is deasserted, the initial chip operating mode is latched from the extboot pin. the internal reset signal will be deasserted synchronous with the internal clocks, after a fixed number of internal clocks. to ensure complete hardware reset, reset and trst should be asserted together. the only exception occurs in a debugging environment when a hardware dsp reset is required and it is necessary not to reset the once/jtag module. in this case, assert reset , but do not assert trst .
gpio signals motorola DSP56F805 preliminary technical data 11 2.6 gpio signals 2.7 pulse width modulator (pwm) signals 1 rsto output output reset output this output reflects the internal reset state of the chip. 1 extboot input input external boot this input is tied to v dd to force device to boot from off-chip memory. otherwise, it is tied to v ss . table 11. dedicated general purpose input/output (gpio) signals no. of pins signal name signal type state during reset signal description 8 gpiob0 C gpiob7 input or output input port b gpio these eight dedicated general purpose i/o (gpio) pins can be individually programmed as input or output pins. after reset, the default state is gpio input. 6 gpiod0 C gpiod5 input or output input port d gpio these six dedicated gpio pins can be individually programmed as an input or output pins. after reset, the default state is gpio input. table 12. pulse width modulator (pwma and pwmb) signals no. of pins signal name signal type state during reset signal description 6 pwma0 C 5 output tri- stated pwma0 C 5 these are six pwma output pins. 3 isa0 C 2 input input isa0 C 2 these three input current status pins are used for top/bottom pulse width correction in complementary channel operation for pwma. 4 faulta0 C 3 input input faulta0 C 3 these four fault input pins are used for disabling selected pwma outputs in cases where fault conditions originate off-chip. 6 pwmb0 C 5 output output pwmb0 C 5 these are six pwmb output pins. 3 isb0 C 2 input input isb0 C 2 these three input current status pins are used for top/bottom pulse width correction in complementary channel operation for pwmb. table 10. interrupt and program control signals (continued) no. of pins signal name signal type state during reset signal description
12 DSP56F805 preliminary technical data motorola 2.8 serial peripheral interface (spi) signals 4 faultb0 C 3 input input faultb0 C 3 these four fault input pins are used for disabling selected pwmb outputs in cases where fault conditions originate off-chip. table 13. serial peripheral interface (spi) signals no. of pins signal name signal type state during reset signal description 1 miso gpioe6 input/ output input/ output input input spi master in/slave out (miso) this serial data pin is an input to a master device and an output from a slave device. the miso line of a slave device is placed in the high-impedance state if the slave device is not selected. port e gpio this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. after reset, the default state is miso. 1 mosi gpioe5 input/ output input/ output input input spi master out/slave in (mosi) this serial data pin is an output from a master device and an input to a slave device. the master device places data on the mosi line a half-cycle before the clock edge that the slave device uses to latch the data. port e gpio this general purpose i/o (gpio) pin can be individually programmed as an input or output pin. after reset, the default state is mosi. 1 sclk gpioe4 input/ output input/ output input input spi serial clock in master mode, this pin serves as an output, clocking slaved listeners. in slave mode, this pin serves as the data clock input. port e gpio this general purpose i/o (gpio) pin can be individually programmed as an input or output pin. after reset, the default state is sclk. 1 ss gpioe7 input input/ output input input spi slave select in master mode, this pin is used to arbitrate multiple masters. in slave mode, this pin is used to select the slave. port e gpio this general purpose i/o (gpio) pin can be individually programmed as input or output pin. after reset, the default state is ss . table 12. pulse width modulator (pwma and pwmb) signals no. of pins signal name signal type state during reset signal description
quadrature decoder signals motorola DSP56F805 preliminary technical data 13 2.9 quadrature decoder signals 2.10 serial communications interface (sci) signals table 14. quadrature decoder (quad dec0 and quad dec1) signals no. of pins signal name signal type state during reset signal description 1 phasea0 ta0 input input/output input input phase a quadrature decoder #0 phasea input ta0 timer a channel 0 1 phaseb0 ta1 input input/output input input phase b quadrature decoder #0 phaseb input ta1 timer a channel 1 1 index0 ta2 input input/output input input index quadrature decoder #0 index input ta2 timer a channel 2 1 home0 ta3 input input/output input input home quadrature decoder #0 home input ta3 timer a channel 3 1 phasea1 tb0 input input/output input input phase a quadrature decoder #1 phasea input tb0 timer b channel 0 1 phaseb1 tb1 input input/output input input phase b quadrature decoder #1 phaseb input tb1 timer b channel 1 1 index1 tb2 input input/output input input index quadrature decoder #1 index input tb2 timer b channel 2 1 home1 tb3 input input/output input input home quadrature decoder #1 home input tb3 timer b channel 3 table 15. serial communications interface (sci0 and sci1) signals no. of pins signal name signal type state during reset signal description 1 txd0 gpioe0 output input/ output input input transmit data (txd0) transmit data output port e gpio this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. after reset, the default state is sci output.
14 DSP56F805 preliminary technical data motorola 2.11 can signals 2.12 analog-to-digital converter (adc) signals 1 rxd0 gpioe1 input input/ output input input receive data (rxd0) receive data input port e gpio this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. after reset, the default state is sci input. 1 txd1 gpiod6 output input/ output input input transmit data (txd1) transmit data output port d gpio this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. after reset, the default state is sci output. 1 rxd1 gpiod7 input input/ output input input receive data (rxd1) receive data input port d gpio this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. after reset, the default state is sci input. table 16. can module signals no. of pins signal name signal type state during reset signal description 1 mscan_ rx input input mscan receive data mscan input. this pin has an internal pull-up resistor. 1 mscan_ tx output output mscan transmit data mscan output. can output is open-drain output and pull-up resistor is needed. table 17. analog to digital converter signals no. of pins signal name signal type state during reset signal description 4 ana0 C 3 input input ana0 C 3 analog inputs to adc channel 1 4 ana4 C 7 input input ana4 C 7 analog inputs to adc channel 2 1 vref input input vref analog reference voltage for adc. must be set to v dda - 0.3v for optimal performance. table 15. serial communications interface (sci0 and sci1) signals (continued) no. of pins signal name signal type state during reset signal description
quad timer module signals motorola DSP56F805 preliminary technical data 15 2.13 quad timer module signals 2.14 jtag/once table 18. quad timer module signals no. of pins signal name signal type state during reset signal description 2 tc0-1 input/ output input tc0 C 1 timer c channels 0 and 1 4 td0-3 input/ output input td0 C 3 timer d channels 0, 1, 2, and 3 table 19. jtag/on-chip emulation (once) signals no. of pins signal name signal type state during reset signal description 1 tck input input, pulled low internally test clock input this input pin provides a gated clock to synchronize the test logic and shift serial data to the jtag/once port. the pin is connected internally to a pull-down resistor. 1 tms input input, pulled high internally test mode select input this input pin is used to sequence the jtag tap controllers state machine. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. 1 tdi input input, pulled high internally test data input this input pin provides a serial input data stream to the jtag/once port. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. 1 tdo output tri-stated test data output this tri-statable output pin provides a serial output data stream from the jtag/once port. it is driven in the shift-ir and shift-dr controller states, and changes on the falling edge of tck. 1 trst input input, pulled high internally test reset as an input, a low signal on this pin provides a reset signal to the jtag tap controller. to ensure complete hardware reset, trst should be asserted whenever reset is asserted. the only exception occurs in a debugging environment when a hardware dsp reset is required and it is necessary not to reset the once/jtag module. in this case, assert reset , but do not assert trst . 1 de output output debug event de provides a low pulse on recognized debug events.
16 DSP56F805 preliminary technical data motorola part 3 specifications 3.1 general characteristics the DSP56F805 is fabricated in high-density cmos with 5-volt tolerant ttl-compatible digital inputs. the term 5-volt tolerant refers to the capability of an i/o pin, built on a 3.3v compatible process technology, to withstand a voltage up to 5.5v without damaging the device. many systems have a mixture of devices designed for 3.3v and 5v power supplies. in such systems, a bus may carry both 3.3v and 5v- compatible i/o voltage levels (a standard 3.3v i/o is designed to receive a maximum voltage of 3.3v 10% during normal operation without causing damage). this 5v tolerant capability therefore offers the power savings of 3.3v i/o levels while being able to receive 5v levels without being damaged. absolute maximum ratings given in table 20 are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond these ratings may affect device reliability or cause permanent damage to the device. the DSP56F805 dc/ac electrical specifications are preliminary and are from design simulations. these specifications may not be fully tested or guaranteed at this early stage of the product life cycle. finalized specifications will be published after complete characterization and device qualifications have been completed. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. table 20. absolute maximum ratings characteristic symbol min max unit supply voltage v dd v ss C 0.3 v ss + 4.0 v all other input voltages, excluding analog inputs, extal and xtal v in v ss C 0.3 v ss + 5.5v v analog inputs, ana0-7 and vref v in v ssa C 0.3 v dda + 0.3 v analog inputs extal and xtal v in v ssa C 0.3 v ssa + 3.0 v current drain per pin excluding v dd , v ss , pwm outputs, tcs, v pp , v dda , v ssa i10ma current drain per pin for pwm outputs i 20 ma junction temperature t j 150c storage temperature range t stg -55 150 c
dc electrical characteristics motorola DSP56F805 preliminary technical data 17 3.2 dc electrical characteristics table 21. recommended operating conditions characteristic symbol min max unit supply voltage v dd, v dda 3.0 3.6 v ambient operating temperature t a -40 85 c table 22. thermal characteristics 1 1. see section 5.1 for more detail. characteristic 144-pin lqfp symbol value unit thermal resistance junction-to-ambient (estimated) q ja 42.7 c/w i/o pin power dissipation p i/o user determined w power dissipation p d p d = (i dd v dd ) + p i/o w maximum allowed p d p dmax (t j C t a ) / q ja c table 23. dc electrical characteristics operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, t a = C40 to +85 c, c l 50 pf, f op = 80 mhz characteristic symbol min typ max unit input high voltage (xtal/extal) v ihc 2.25 2.5 2.75 v input low voltage (xtal/extal) v ilc 0 0.5 v input high voltage v ih 2.0 5.5 v input low voltage v il -0.3 0.8 v input current low (pullups/pulldowns disabled) i il -1 1 m a input current high (pullups/pulldowns disabled) i ih -1 1 m a typical pullup or pulldown resistance r pu , r pd 30 k w output tri-state current low i ozl -10 10 m a output tri-state current high i ozh -10 10 m a output high voltage with ioh load v oh v dd C 0.7 v output low voltage with iol load v ol 0.4 v output high current i oh -4 ma
18 DSP56F805 preliminary technical data motorola output low current i ol 4 ma input capacitance c in 8pf output capacitance c out 12 pf pwm pin output source current 1 i ohp -10 ma pwm pin output sink current 2 i olp 16ma total supply current i ddt 3 run 4 126 162 ma wait 5 7298ma stop 6084ma low voltage interrupt 6 v ei 2.4 2.7 2.9 v power on reset 7 v por 1.72.0 v 1. pwm pin output source current measured with 50% duty cycle. 2. pwm pin output sink current measured with 50% duty cycle. 3. i ddt = i dd + i dda (total supply current for v dd + v dda ) 4. run (operating) i dd measured using 8mhz clock source. all inputs 0.2v from rail; outputs unloaded. all ports configured as inputs; measured with all modules enabled. 5. wait i dd measured using external square wave clock source (f osc = 8 mhz) into xtal; all inputs 0.2v from rail; no dc loads; less than 50 pf on all outputs. c l = 20 pf on extal; all ports configured as inputs; extal capacitance linearly affects wait i dd ; measured with pll enabled. 6. low voltage interrupt monitors the v dda supply. when v dda drops below v ei value, an interrupt is generated. for correct operation, set v dda =v dd . functionality of the device is guaranteed under transient conditions when v dda > v ei . 7. power-on reset occurs whenever the internally regulated 2.5v digital supply drops below v por . while power is ramping up, this signal remains active for as long as the internal 2.5v supply is below 1.5v no matter how long the ramp up rate is. the internally regulated voltage is typically 100 mv less than v dd during ramp up until 2.5v is reached, at which time it self regulates. table 23. dc electrical characteristics (continued) operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, t a = C40 to +85 c, c l 50 pf, f op = 80 mhz characteristic symbol min typ max unit
ac electrical characteristics motorola DSP56F805 preliminary technical data 19 figure 3. maximum run idd vs. frequency (see note 4 above) 3.3 ac electrical characteristics timing waveforms in section 3.3 are tested with a v il maximum of 0.8 v and a v ih minimum of 2.0 v for all pins except xtal, which is tested using the input levels in section 3.2 . in figure 4 the levels of v ih and v il for an input signal are shown. figure 4. input signal measurement references figure 5 shows the definitions of the following signal states: ? active state, when a bus or signal is driven, and enters a low impedance state. ? tri-stated, when a bus or signal is placed in a high impedance state. ? data valid state, when a signal level has reached v ol or v oh. ? data invalid state, when a signal level is in transition between v ol and v oh. 180 150 120 90 60 30 0 idd (ma) digital (vdd=3.6v) analog (vdda=3.6v) total freq. (mhz) 0 40 60 80 20 v ih v il fall time input signal note: the midpoint is v il + (v ih C v il )/2. midpoint1 low high 90% 50% 10% rise time
20 DSP56F805 preliminary technical data motorola 3.4 flash memory characteristics figure 5. signal states table 24. flash memory truth table mode xe 1 1. x address enable, all rows are disabled when xe = 0 ye 2 2. y address enable, ymux is disabled when ye = 0 se 3 3. sense amplifier enable oe 4 4. output enable, tri-state flash data out bus when oe = 0 prog 5 5. defines program cycle erase 6 6. defines erase cycle mas1 7 7. defines mass erase cycle, erase whole block nvstr 8 8. defines non-volatile store cycle standby l l l l l l l l read h h h h l l l l word program h h l l h l l h page erase h l l l l h l h mass erase h l l l l h h h table 25. ifren truth table mode ifren = 1 ifren = 0 read read information block read main memory block word program program information block program main memory block page erase erase information block erase main memory block mass erase erase both block erase main memory block data invalid state data1 data2 valid data tri-stated data3 valid data2 data3 data1 valid data active data active
flash memory characteristics motorola DSP56F805 preliminary technical data 21 *the flash interface unit provides registers for the control of these parameters. table 26. timing symbols characteristic symbol see figure(s) prog/erase to nvstr set up time t nvs* figure 6 , figure 7 , figure 8 nvstr hold time t nvh* figure 6 , figure 7 nvstr hold time(mass erase) t nvh1* figure 8 nvstr to program set up time t pgs* figure 6 program hold time t pgh figure 6 address/data set up time t ads figure 6 address/data hold time t adh figure 6 recovery time t rcv* figure 6 , figure 7 , figure 8 cumulative program hv period t hv figure 6 program time t prog* figure 6 erase time t erase* figure 7 mass erase time t me* figure 8 table 27. flash timing parameters operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, t a = C40 to +85 c, c l 50 pf characteristic symbol min typ max unit program time t prog 20 us erase time t erase 20 ms mass erase time t me 100 ms endurance 1 e cyc 10,000 20,000 cycles data retention 1 @ 5,000 cycles d ret 10 30 years the following parameters should only be used in the manual word programming mode. prog/erase to nvstr set up time t nvs 5 us nvstr hold time t nvh 5 us nvstr hold time(mass erase) t nvh1 100 us
22 DSP56F805 preliminary technical data motorola figure 6. flash program cycle nvstr to program set up time t pgs 10us recovery time t rcv 1 us cumulative program hv period t hv 3 ms 1. program specification guaranteed from t a = 0 c to 85 c. table 27. flash timing parameters (continued) operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, t a = C40 to +85 c, c l 50 pf xadr yadr ye din prog nvstr tnvs tpgs tadh tprog tads tpgh tnvh trcv thv ifren xe
flash memory characteristics motorola DSP56F805 preliminary technical data 23 figure 7. flash erase cycle figure 8. flash mass erase cycle xadr ye=se=oe=mas1=0 erase nvstr tnvs tnvh trcv terase ifren xe xadr ye=se=oe=0 erase nvstr tnvs tnvh1 trcv tme mas1 ifren xe
24 DSP56F805 preliminary technical data motorola 3.5 external clock operation the DSP56F805 system clock can be derived from a crystal or an external system clock signal. to generate a reference frequency using the internal oscillator, a reference crystal must be connected between the extal and xtal pins. 3.5.1 crystal oscillator the internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in table 29 . in figure 9 a typical crystal oscillator circuit is shown. follow the crystal suppliers recommendations when selecting a crystal, because crystal parameters determine the component values required to provide maximum stability and reliable start-up. the crystal and associated components should be mounted as close as possible to the extal and xtal pins to minimize output distortion and start-up stabilization time. figure 9. connecting to a crystal oscillator 3.5.2 ceramic resonator it is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system design can tolerate the reduced signal integrity. in figure 10 , a typical ceramic resonator circuit is shown. refer to suppliers recommendations when selecting a ceramic resonator and associated components. the resonator and components should be mounted as close as possible to the extal and xtal pins. figure 10. connecting a ceramic resonator 3.5.3 external clock source the recommended method of connecting an external clock is given in figure 12 . the external clock source is connected to xtal and the extal pin is grounded. figure 11. connecting an external clock signal sample external crystal parameters: r z = 10 m w f c = 4-8 mhz (optimized for 8 mhz) extal xtal r z f c sample ceramic resonator parameters r z = 10 m w f c = 4-8 mhz (optimized for 8 mhz) extal xtal r z f c DSP56F805 xtal extal external v ss clock
external clock operation motorola DSP56F805 preliminary technical data 25 figure 12. external clock timing table 28. external clock operation timing requirements 5 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, t a = C40 to +85 c characteristic symbol min typ max unit frequency of operation (external clock driver) 1 1. see figure for details on using the recommended connection of an external clock driver. f osc 0880mhz clock pulse width 2 , 5 2. the high or low pulse width must be no smaller than 6.25 ns or the chip will not function. t pw 6.25 ns external clock input rise time 3 , 5 3. external clock input rise time is measured from 10% to 90%. t rise 3ns external clock input fall time 4 , 5 4. external clock input fall time is measured from 90% to 10%. 5. parameters listed are guaranteed by design. t fall 3ns table 29. pll timing operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, t a = C40 to +85 c characteristic symbol min typ max unit external reference crystal frequency for the pll 1 1. an externally supplied reference clock should be as free as possible from any phase jitter for the pll to work correctly. the pll is optimized for 8 mhz input crystal.2. f osc 488mhz pll output frequency 2 (f out /2) 2. zclk may not exceed 80 mhz. for additional information on zclk and f out /2, please refer to the occs chapter in the user manual. f op 40 110mhz pll stabilization time 3 0 o to +85 o c 3. this is the minimum time required after the pll setup is changed to ensure reliable operation. t plls 110ms pll stabilization time 3 -40 o to 0 o c t plls 100 200 ms external clock v ih v il note: the midpoint is v il + (v ih C v il )/2. 90% 50% 10% 90% 50% 10% t pw t pw t fall t rise
26 DSP56F805 preliminary technical data motorola 3.6 external bus asynchronous timing table 30. external bus asynchronous timing 1, 2 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, t a = C40 to +85 c, c l 50 pf, f op = 80 mhz 1. timing is both wait state and frequency dependent. in the formulas listed, ws = the number of wait states and t = clock period. for 80 mhz operation, t = 12.5ns. 2. parameters listed are guaranteed by design. to calculate the required access time for an external memory for any frequency < 80 mhz, use this formula: top = clock period @ desired operating frequency ws = number of wait states memory access time = (top*ws) + (top- 11.5) characteristic symbol typical min typical max unit address valid to wr asserted t awr 6.5 ns wr width asserted wait states = 0 wait states > 0 t wr 7.5 (t*ws)+7.5 ns ns wr asserted to d0Cd15 out valid t wrd t+4.2ns data out hold time from wr deasserted t doh 4.8 ns data out set up time to wr deasserted wait states = 0 wait states > 0 t dos 2.2 (t*ws)+6.4 ns ns rd deasserted to address not valid t rda 0ns address valid to rd deasserted wait states = 0 wait states > 0 t ardd 18.7 (t*ws) + 18.7 ns ns input data hold to rd deasserted t drd 0ns rd assertion width wait states = 0 wait states > 0 t rd 19 (t*ws)+19 ns ns address valid to input data valid wait states = 0 wait states > 0 t ad 1 (t*ws)+1 ns ns address valid to rd asserted t arda -4.4 ns rd asserted to input data valid wait states = 0 wait states > 0 t rdd 2.4 (t*ws) + 2.4 ns ns wr deasserted to rd asserted t wrrd 6.8 ns rd deasserted to rd asserted t rdrd 0ns wr deasserted to wr asserted t wrwr 14.1 ns rd deasserted to wr asserted t rdwr 12.8 ns
reset, stop, wait, mode select, and interrupt timing motorola DSP56F805 preliminary technical data 27 3.7 reset, stop, wait, mode select, and interrupt timing figure 13. external bus asynchronous timing table 31. reset, stop, wait, mode select, and interrupt timing 1, 6 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, t a = C40 to +85 c, c l 50 pf characteristic symbol typical min typical max unit see figure reset assertion to address, data and control signals high impedance t raz 21ns figure 14 minimum reset assertion duration 2 omr bit 6 = 0 omr bit 6 = 1 t ra 275,000t 128t ns ns figure 14 reset de-assertion to first external address output t rda 33t 34t ns figure 14 edge-sensitive interrupt request width t irw 1.5t ns figure 15 irqa , irqb assertion to external data memory access out valid, caused by first instruction execution in the interrupt service routine t idm 15t ns figure 16 irqa , irqb assertion to general purpose output valid, caused by first instruction execution in the interrupt service routine t ig 16t ns figure 16 irqa low to first valid interrupt vector address out recovery from wait state 3 t iri 13t ns figure 17 a0Ca15, ps , ds (see note) wr d0Cd15 rd note: during read-modify-write instructions and internal instructions, the address lines do not change state. data in data out t awr t arda t ardd t rda t rd t rdrd t rdwr t wrwr t wr t dos t wrd t wrrd t ad t doh t drd t rdd
28 DSP56F805 preliminary technical data motorola figure 14. asynchronous reset timing irqa width assertion to recover from stop state 4 t iw 2tns figure 18 delay from irqa assertion to fetch of first instruction (exiting stop) omr bit 6 = 0 omr bit 6 = 1 t if 275,000t 12t ns ns figure 18 duration for level sensitive irqa assertion to cause the fetch of first irqa interrupt instruction (exiting stop) omr bit 6 = 0 omr bit 6 = 1 t irq 275,000t 12t ns ns figure 19 delay from level sensitive irqa assertion to first interrupt vector address out valid (exiting stop) omr bit 6 = 0 omr bit 6 = 1 t ii 275,000t 12t ns ns figure 19 rsto pulse width 5 normal operation internal reset mode t rsto 63et 2,097,151et ns ns figure 20 1. in the formulas, t = clock cycle. for an operating frequency of 80 mhz, t = 12.5 ns. 2. circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases: ? after power-on reset ? when recovering from stop state 3. the minimum is specified for the duration of an edge-sensitive irqa interrupt required to recover from the stop state. this is not the minimum required so that the irqa interrupt is accepted. 4. the interrupt instruction fetch is visible on the pins only in mode 3. 5. et = external clock period, for an external crystal frequency of 8 mhz, et=125 ns. 6. parameters listed are guaranteed by design. table 31. reset, stop, wait, mode select, and interrupt timing 1, 6 (continued) operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, t a = C40 to +85 c, c l 50 pf characteristic symbol typical min typical max unit see figure first fetch a0Ca15, d0Cd15 ps , ds , rd , wr reset first fetch t rda t ra t raz
reset, stop, wait, mode select, and interrupt timing motorola DSP56F805 preliminary technical data 29 figure 15. external interrupt timing (negative-edge-sensitive) figure 16. external level-sensitive interrupt timing figure 17. interrupt from wait state timing irqa irqb t irw a0Ca15, ps , ds , rd , wr irqa , irqb first interrupt instruction execution a) first interrupt instruction execution purpose i/o pin irqa , irqb b) general purpose i/o t ig t idm instruction fetch irqa , irqb first interrupt vector a0Ca15, ps , ds , rd , wr t iri
30 DSP56F805 preliminary technical data motorola figure 18. recovery from stop state using asynchronous interrupt timing figure 19. recovery from stop state using irqa interrupt service figure 20. reset output timing 3.8 serial peripheral interface (spi) timing table 32. spi timing 1 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, t a = C40 to +85 c, c l 50 pf, f op = 80 mhz characteristic symbol min max unit see figure cycle time master slave t c 50 25 ns ns figures 21 , 22 , 23 , 24 enable lead time master slave t eld 25 ns ns figure 24 not irqa interrupt vector irqa a0Ca15, ps , ds , rd , wr first instruction fetch t iw t if instruction fetch irqa a0Ca15 ps , ds , rd , wr first irqa interrupt t irq t ii rsto t rsto
serial peripheral interface (spi) timing motorola DSP56F805 preliminary technical data 31 1. parameters listed are guaranteed by design. enable lag time master slave t elg 100 ns ns figure 24 clock (sclk) high time master slave t ch 17.6 12.5 ns ns figures 21 , 22 , 23 , 24 clock (sclk) low time master slave t cl 24.1 25 ns ns figure 24 data setup time required for inputs master slave t ds 20 0 ns ns figures 21 , 22 , 23 , 24 data hold time required for inputs master slave t dh 0 2 ns ns figures 21 , 22 , 23 , 24 access time (time to data active from high- impedance state) slave t a 4.8 15 ns figure 24 disable time (hold time to high-impedance state) slave t d 3.7 15.2 ns figure 24 data valid for outputs master slave (after enable edge) t dv 4.5 20.4 ns ns figures 21 , 22 , 23 , 24 data invalid master slave t di 0 0 ns ns figures 21 , 22 , 23 , 24 rise time master slave t r 11.5 10.0 ns ns figures 21 , 22 , 23 , 24 fall time master slave t f 9.7 9.0 ns ns figures 21 , 22 , 23 , 24 table 32. spi timing 1 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, t a = C40 to +85 c, c l 50 pf, f op = 80 mhz
32 DSP56F805 preliminary technical data motorola figure 21. spi master timing (cpha = 0) figure 22. spi master timing (cpha = 1) sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14C1 lsb in master msb out bits 14C1 master lsb out ss (input) ss is held high on master t c t r t f t ch t cl t f t r t ch t ch t dv t dh t ds t di t di (ref) t f t r t cl sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14C1 lsb in master msb out bits 14C 1 master lsb out ss (input) ss is held high on master t r t f t c t ch t cl t ch t cl t f t ds t dh t r t di t dv (ref) t dv t f t r
serial peripheral interface (spi) timing motorola DSP56F805 preliminary technical data 33 figure 23. spi slave timing (cpha = 0) figure 24. spi slave timing (cpha = 1) sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14C1 msb in bits 14C1 lsb in ss (input) slave lsb out t ds t cl t cl t di t di t ch t ch t r t r t elg t dh t eld t c t f t f t d t a t dv sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14C1 msb in bits 14C1 lsb in ss (input) slave lsb out t elg t di t ds t dh t eld t c t cl t ch t r t f t f t cl t ch t dv t a t dv t r t d
34 DSP56F805 preliminary technical data motorola 3.9 quad timer timing 3.10 quadrature decoder timing table 33. timer timing 1, 2 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, t a = C40 to +85 c, c l 50 pf, f op = 80 mhz 1. in the formulas listed, t = clock cycle. for 80 mhz operation, t = 12.5 ns. 2. parameters listed are guaranteed by design. characteristic symbol typical min typical max unit timer input period p in 4t+6 ns timer input high/low period p inhl 2t+3 ns timer output period p out 2t ns timer output high/low period p outhl 1t ns figure 25. timer timing table 34. quadrature decoder timing 1, 2 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, t a = C40 to +85 c, c l 50 pf, f op = 80 mhz 1. in the formulas listed, t = clock cycle. for 80 mhz operation, t = 12.5 ns. v ss = 0 v, v dd = 3.0C3.6 v, t a = C40 to +85 c, c l 50 pf. 2. parameters listed are guaranteed by design. characteristic symbol typical min typical max unit quadrature input period p in 8t+12 ns quadrature input high/low period p hl 4t+6 ns quadrature phase period p ph 2t+3 ns timer inputs timer outputs p inhl p inhl p in p outhl p outhl p out
serial communication interface (sci) timing motorola DSP56F805 preliminary technical data 35 3.11 serial communication interface (sci) timing figure 27. rxd pulse width figure 26. quadrature decoder timing table 35. sci timing 4 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, t a = C40 to +85 c, c l 50 pf, f op = 80 mhz characteristic symbol min max unit baud rate 1 1. f max is the frequency of operation of the system clock in mhz. br (f max *2.5)/(80) mbps rxd 2 pulse width 2. the rxd pin in sci0 is named rxd0 and the rxd pin in sci1 is named rxd1. rxd pw 0.965/br 1.04/br ns txd 3 pulse width 3. the txd pin in sci0 is named txd0 and the txd pin in sci1 is named txd1. 4. parameters listed are guaranteed by design. txd pw 0.965/br 1.04/br ns phase b (input) phase a (input) p ph p ph p ph p ph p in p in p hl p hl p hl p hl rxd sci receive data pin (input) rxd pw
36 DSP56F805 preliminary technical data motorola figure 28. txd pulse width 3.12 analog-to-digital converter (adc) characteristics table 36. adc characteristics operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, v ref = v dd -0.3v, adcdiv = 4, 9, or 14, adc clock = 4mhz, 3.0C3.6 v, t a = C40 to +85 c, c l 50 pf, f op = 80 mhz characteristic symbol min typ max unit input voltages v adin 0 v dda 1 1. v dda should be tied to the same potential as v dd via separate traces. v ref must be equal to or less than v dd and must be greater than or equal to 2.7v. v resolution r es 12 12 bits integral non-linearity 2 2. . measured in 10-90% range. inl +/-2.5 +/-4 lsb 3 3. lsb = least significant bit. differential non-linearity dnl +/- 0.9 +/-1 lsb 3 monotonicity guaranteed adc internal clock f adic 0.5 5 mhz conversion range r ad v ssa v dda v conversion time t adc 6 t aic cycles 4 sample time t ads 1 t aic cycles 4 input capacitance c adi 5 pf 4 gain error (transfer gain) e gain .95 1.00 1.10 offset voltage v offset -80 -15 +20 mv total harmonic distortion thd 60 64 db signal-to-noise plus distortion sinad 55 60 db effective number of bits enob 9 10 bit spurious free dynamic range sfdr 65 70 db bandwidth bw 100 khz adc quiescent current (both adcs) i adc 39.3 ma v ref quiescent current (both adcs) i vref 11.85 14.5 ma txd sci receive data pin (input) txd pw
controller area network (can) timing motorola DSP56F805 preliminary technical data 37 figure 29. equivalent analog input circuit 1. parasitic capacitance due to package, pin to pin, and pin to package base coupling. 1.8pf 2. parasitic capacitance due to the chip bond pad, esd protection devices and signal routing. 2.04pf 3. equivalent resistance for the esd isolation resistor and the channel select mux. 500 ohms 4. sampling capacitor at the sample and hold circuit. 1pf 3.13 controller area network (can) timing figure 30. bus wakeup detection table 37. can timing 2 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, t a = C40 to +85 c, c l 50 pf, mscan clock = 30 mhz characteristic symbol min max unit baud rate br can 1 mbps bus wakeup detection 1 1. if wakeup glitch filter is enabled during the design initialization and also can is put into sleep mode then, any bus event (on mscan_rx pin) whose duration is less than 5 microseconds is filtered away. however, a valid can bus wakeup detection takes place for a wakeup pulse equal to or greater than 5 microseconds. the number 5 microseconds originates from the fact that the can wakeup message consists of 5 dominant bits at the highest possible baud rate of 1 mbps. 2. parameters listed are guaranteed by design. t wakeup 5us 1 2 3 4 adc analog input mscan_rx can receive data pin (input) t wakeup
38 DSP56F805 preliminary technical data motorola 3.14 jtag timing table 38. jtag timing 1, 3 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, t a = C40 to +85 c, c l 50 pf, f op = 80 mhz 1. timing is both wait state and frequency dependent. for the values listed, t = clock cycle. for 80 mhz operation, t = 12.5 ns. characteristic symbol min max unit tck frequency of operation 2 2. tck frequency of operation must be less than 1/8 the processor rate. 3. parameters listed are guaranteed by design. f op dc 10 mhz tck cycle time t cy 100 ns tck clock pulse width t pw 50 ns tms, tdi data setup time t ds 0.4 ns tms, tdi data hold time t dh 1.2 ns tck low to tdo data valid t dv 26.6 ns tck low to tdo tri-state t ts 23.5 ns trst assertion time t trst 50 ns de assertion time t de 4t ns figure 31. test clock input timing diagram tck (input) v m v il v m = v il + (v ih C v il )/2 v m v ih t pw t pw t cy
jtag timing motorola DSP56F805 preliminary technical data 39 figure 32. test access port timing diagram figure 33. trst timing diagram figure 34. oncedebug event input data valid output data valid output data valid tck (input) tdi (input) tdo (output) tdo (output ) tdo (output) tms t dv t ts t dv t ds t dh trst (input) t trst de t de
40 DSP56F805 preliminary technical data motorola part 4 packaging 4.1 package and pin-out information DSP56F805 this section contains package and pin-out information for the 144-pin lqfp configuration of the DSP56F805. figure 35. top view, DSP56F805 144-pin lqfp package orientation mark 1 37 73 109 d10 d11 d12 d13 d14 d15 a0 vdd pwmb0 vss pwmb1 a1 pwmb2 a2 pwmb3 a3 a4 a5 pwmb4 a6 pwmb5 a7 isb0 a8 isb1 a9 isb2 a10 faultb0 a11 faultb1 a12 a13 vdd ps ds rxd0 txd0 pwma5 pwma4 gpiod2 pwma3 gpiod1 pwma2 gpiod0 pwma1 gpiob7 pwma0 gpiob6 home0 gpiob5 index0 gpiob4 vss gpiob3 vdd gpiob2 phaseb0 gpiob1 phasea0 gpiob0 vss vdd vdd vdda vssa extal xtal ana7 ana6 ana5 ana4 144 motorola DSP56F805 extboot reset de clko td0 td1 vdd td2 vss td3 rsto ss gpiod3 miso gpiod4 mosi sclk vcapc gpiod5 d0 vpp d1 d2 index1 vdd phaseb1 vss phasea1 d3 home1 d4 d5 d6 d7 d8 d9 ana3 ana2 ana1 ana0 vref faulta3 faulta2 mscan_rx faulta1 mscan_tx faulta0 rxd1 isa2 vss isa1 vdd isa0 vcapc trst tdo txd1 tdi tc1 tms tc0 tck faultb3 tcs faultb2 irqb irqa rd wr vss a15 a14
package and pin-out information DSP56F805 motorola DSP56F805 preliminary technical data 41 table 39. DSP56F805 pin identification by pin number pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1 d10 37 a14 73 ana4 109 extboot 2 d11 38 a15 74 ana5 110 reset 3 d12 39 v ss 75 ana6 111 de 4 d13 40 wr 76 ana7 112 clko 5 d14 41 rd 77 xtal 113 td0 6 d15 42 irqa 78 extal 114 td1 7a043irqb 79 v ssa 115 v dd 8v dd 44 faultb2 80 v dda 116 td2 9pwmb045 tcs 81 v dd 117 v ss 10 v ss 46 faultb3 82 v dd 118 td3 11 pwmb1 47 tck 83 v ss 119 rsto 12 a1 48 tc0 84 gpiob0 120 ss 13 pwmb2 49 tms 85 phasea0 121 gpiod3 14 a2 50 tc1 86 gpiob1 122 miso 15 pwmb3 51 tdi 87 phaseb0 123 gpiod4 16 a3 52 txd1 88 gpiob2 124 mosi 17 a4 53 tdo 89 v dd 125 sclk 18 a5 54 trst 90 gpiob3 126 vcapc 19 pwmb4 55 vcapc 91 v ss 127 gpiod5 20 a6 56 isa0 92 gpiob4 128 d0 21 pwmb5 57 v dd 93 index0 129 vpp 22 a7 58 isa1 94 gpiob5 130 d1 23 isb0 59 v ss 95 home0 131 d2 24 a8 60 isa2 96 gpiob6 132 index1 25 isb1 61 rxd1 97 pwma0 133 v dd 26 a9 62 faulta0 98 gpiob7 134 phaseb1 27 isb2 63 mscan_tx 99 pwma1 135 v ss
42 DSP56F805 preliminary technical data motorola 28 a10 64 faulta1 100 gpiod0 136 phasea1 29 faultb0 65 mscan_rx 101 pwma2 137 d3 30 a11 66 faulta2 102 gpiod1 138 home1 31 faultb1 67 faulta3 103 pwma3 139 d4 32 a12 68 vref 104 gpiod2 140 d5 33 a13 69 ana0 105 pwma4 141 d6 34 v dd 70 ana1 106 pwma5 142 d7 35 ps 71 ana2 107 txd0 143 d8 36 ds 72 ana3 108 rxd0 144 d9 table 39. DSP56F805 pin identification by pin number (continued) pin no. signal name pin no. signal name pin no. signal name pin no. signal name
package and pin-out information DSP56F805 motorola DSP56F805 preliminary technical data 43 figure 36. 144-pin lqfp mechanical information
44 DSP56F805 preliminary technical data motorola part 5 design considerations 5.1 thermal design considerations an estimation of the chip junction temperature, t j , in c can be obtained from the equation: equation 1: where: t a = ambient temperature c r q ja = package junction-to-ambient thermal resistance c/w p d = power dissipation in package historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: equation 2: where: r q ja = package junction-to-ambient thermal resistance c/w r q jc = package junction-to-case thermal resistance c/w r q ca = package case-to-ambient thermal resistance c/w r q jc is device-related and cannot be influenced by the user. the user controls the thermal environment to change the case-to-ambient thermal resistance, r q ca . for example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board (pcb), or otherwise change the thermal dissipation capability of the area surrounding the device on the pcb. this model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. for ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the pcb, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. the thermal performance of plastic packages is more dependent on the temperature of the pcb to which the package is mounted. again, if the estimations obtained from r q ja do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. definitions: a complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages: ? measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. this is done to minimize temperature variation across the surface. ? measure the thermal resistance from the junction to where the leads are attached to the case. this definition is approximately equal to a junction to board thermal resistance. t j t a p d r q ja () + = r q ja r q jc r q ca + =
electrical design considerations motorola DSP56F805 preliminary technical data 45 ? use the value obtained by the equation (t j C t t )/p d where t t is the temperature of the package case determined by a thermocouple. the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition on page 45. from a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. in natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual. hence, the new thermal metric, thermal characterization parameter, or y jt , has been defined to be (t j C t t )/p d . this value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. the recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. 5.2 electrical design considerations use the following list of considerations to assure correct dsp operation: ? provide a low-impedance path from the board power supply to each v dd pin on the dsp, and from the board ground to each v ss pin. ? the minimum bypass requirement is to place six 0.01C0.1 m f capacitors positioned as close as possible to the package supply pins. the recommended bypass configuration is to place one bypass capacitor on each of the nine v dd /v ss pairs, including v dda /v ssa. the vcap capacitors must be 150 milliohm or less esr capacitors. ? ensure that capacitor leads and associated printed circuit traces that connect to the chip v dd and v ss pins are less than 0.5 inch per capacitor lead. ? use at least a four-layer printed circuit board (pcb) with two inner layers for v dd and v ss . ? bypass the v dd and v ss layers of the pcb with approximately 100 m f, preferably with a high- grade capacitor such as a tantalum capacitor. ? because the dsp output signals have fast rise and fall times, pcb trace lengths should be minimal. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
46 DSP56F805 preliminary technical data motorola ? consider all device loads as well as parasitic capacitance due to pcb traces when calculating capacitance. this is especially critical in systems with higher capacitive loads that could create higher transient currents in the v dd and v ss circuits. ? take special care to minimize noise levels on the vref, v dda and v ssa pins. ? designs that utilize the trst pin for jtag port or once module functionality (such as development or debugging systems) should allow a means to assert trst whenever reset is asserted, as well as a means to assert trst independently of reset . designs that do not require debugging functionality, such as consumer products, should tie these pins together. ? trst must be externally asserted even when the user relies on the internal power on reset for functional test purposes. ? because the flash memory is programmed through the jtag/once port, designers should provide an interface to this port to allow in-circuit flash programming.
electrical design considerations motorola DSP56F805 preliminary technical data 47 part 6 ordering information table 40 lists the pertinent information needed to place an order. consult a motorola semiconductor sales office or authorized distributor to determine availability and to order parts. table 40. DSP56F805 ordering information part supply voltage package type pin count frequency (mhz) order number DSP56F805 3.0C3.6 v low profile plastic quad flat pack (lqfp) 144 80 DSP56F805fv80
DSP56F805/d motorola and the stylized m logo are registered in the us patent & trademark office. all other product or service names are the property of their respective owners. ? motorola, inc. 2002. how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217. 1C303C675C2140 or 1C800C441C2447 japan: motorola japan ltd.; sps, technical information center, 3C20C1, minamiCazabu. minatoCku, tokyo 106C8573 japan. 81C3C3440C3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kon g . 852C26668334 technical information center: 1C800C521C6274 home page: http://www.motorola.com/semiconductors/ motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application o r use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical param eters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all oper ating parameters, including typicals must be validated for each customer application by customers technical experts. motorola does not convey any licens e under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for sur gical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product cou ld create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer s hall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expens es, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer.

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